How do you transition from today’s 2.5D systems into tomorrow’s true 3D IC architectures — while balancing cost, performance, and thermal demands? What you’ll learn… Where hyperscalers and AI accelerator developers are leading the 3D IC adoption curve. Why design enablement and ecosystems are still evolving for mainstream adoption. The tipping points that push companies toward 2.5D/3D IC designs. The new methodology requirements: system-centric, predictive, shift-left modeling. Why siloed design teams can’t meet the demands of advanced 3D IC. How Siemens’ portfolio and AE expertise help customers adapt tools, methods, and organizations for success. What you’ll discover… (01:40) Current state of 3D IC adoption: hyperscalers, AI accelerators, and beyond. (04:20) 3D VS 2.5D design and (hybrid bonding, stacking, bridges). (05:30) Why customers want to learn more about 3D IC design. (06:50) Why do customers move over to 3D IC design? (08:25) Challenges in 3D IC design. (10:20) Methodology shifts: early system-level planning and predictive modeling (13:30) Siemens’ broad portfolio, roadmap collaboration, and multi-physics modeling (15:45) The 5-year outlook: chiplet standards, system-on-wafer, and power/thermal battles More about this episode… In this episode of the Siemens 3D IC Podcast, host John McMillan speaks with Kevin Rinebold, 3D IC Packaging and Account Technology Manager at Siemens EDA. With over 35 years of customer-facing experience, Kevin shares insights into the evolution of advanced packaging, chiplet integration, and the methodologies needed for the next wave of 3D IC adoption. The discussion covers how hyperscalers are driving AI and high-performance compute with 2.5D and emerging 3D approaches, why design enablement remains uneven across the supply chain, and what’s required to balance thermal, power, and signal considerations at scale. Kevin emphasizes that 3D IC isn’t just a technical challenge; it’s an organizational shift toward integrated, cross-disciplinary collaboration. He also highlights Siemens’ role in enabling customers to “shift left,” evaluate tradeoffs early, and leverage a broad portfolio of tools and expertise to meet the complexity of future 3D IC designs. Looking ahead, Kevin points to maturing chiplet standards, system-on-wafer architectures, and the ongoing battle to get power in and heat out of dense 3D IC stacks. Ideal for: IC packaging engineers, 3D IC architects, chiplet designers, substrate fabricators, and verification professionals navigating the shift from 2.5D to 3D integration. Connect with John McMillan LinkedIn Website Connect with Kevin Rinebold LinkedIn Website
How do you ensure that cutting-edge 3D IC designs can actually be manufactured before investing millions in production? What you’ll learn… What test vehicles are and why they’re indispensable for validating manufacturability How daisy chain structures pinpoint weaknesses in bumps, balls, and die connections Who builds test vehicles: OSATs, foundries, or customers, and why it matters How test vehicles strengthen collaboration between OEMs and OSATs The hidden value of test vehicles in reliability, regulatory compliance, and risk mitigation Where you’ll find it…. (02:00) What a test vehicle is when it’s needed (03:20) Real-world example: testing embedded chips before mass production (06:00) Who’s responsible for creating test vehicles? (07:20) How do test vehicles factor into the relationship between the OSATs and the OEMs? (09:25) The link between test vehicles and PCB design practices (11:12) Beyond connectivity: heaters, capacitive structures, and stacked vias (15:25) Automotive and regulatory requirements for reliability testing (17:15) Why engineers shouldn’t design daisy chains by hand More about this episode… In this episode of the Siemens 3D IC Podcast, host John McMillan talks with Kendall Hiles, Senior 3D IC Product Specialist at Siemens EDA, about the critical role of test vehicles and daisy chain design tests in semiconductor innovation. Unlike a final product, a test vehicle isn’t built to sell, it’s built to learn. Kendall Hiles explains how test vehicles act as manufacturing “test beds,” enabling engineers to validate new processes and technologies before scaling up to costly production runs. The conversation dives into daisy chain design tests, a clever way of stringing together bumps and balls to measure connectivity and identify failure points with precision. Kendall also highlights when OSATs, foundries, or customers should take ownership of creating test vehicles, and how they factor into collaboration between OEMs and manufacturers. Listeners will also hear why test vehicles are especially vital for automotive reliability and regulatory compliance, and why manual spreadsheet-driven daisy chain design is a risky practice in today’s complex 3D IC world. For anyone working in semiconductor packaging, 3D IC design, or advanced manufacturing, this episode offers practical insight into improving yield, reducing risk, and accelerating innovation. Connect with John McMillan LinkedIn Website Connect with Kendall Hiles LinkedIn Website
How do you design and verify a package with tens of millions of pins — without losing months to manual rework? What you’ll learn… Why chiplet-based architectures demand new approaches to IC packaging How hierarchical device planning reduces overwhelming complexity The risks of spreadsheet-based workflows and why they’re no longer viable How early, multi-domain analysis helps avoid costly late-stage redesigns What Siemens’ Innovator 3D IC Portfolio offers for synchronized, error-proof design Where you’ll find it…. (01:50) Current changes in IC Packaging and the impact on the whole ecosystem (03:00) How to manage complexity scaling (03:35) What hierarchical device planning is and why it matters (05:00) How traditional methods fall short for high-pin-count designs (06:20) The risks and consequences of package assembly errors (07:00) What next-gen tools must deliver for designers (09:10) Siemens’ Innovator 3D IC Portfolio overview More about this episode… In this episode of the Siemens 3D IC Podcast, host John McMillan speaks with Per Viklund, Director of IC Packaging and RF Product Lines at Siemens EDA, about the growing challenge of managing chiplet and interposer complexity in advanced 3D IC designs. Per explains how hierarchical device planning enables designers to work at the right level of abstraction, streamlining the creation, optimization, and verification of massive, high-pin-count packages. The discussion covers why spreadsheet-based methods no longer cut it, the risks of unsynchronized workflows, and how early, multi-domain analysis can prevent costly late-stage redesigns. The episode also introduces Siemens’ Innovator 3D IC Portfolio — a unified, AI-infused solution designed to support the entire packaging workflow, from early planning through final layout, with built-in data management to eliminate version errors. Ideal for IC packaging engineers, 3D IC architects, chiplet designers, substrate fabricators, and verification professionals working on high-complexity designs. Connect with John McMillan LinkedIn Website Connect with Per Viklund LinkedIn Website
How do you ensure clean, stable power and reliable signal transmission in a dense 3D IC stack without introducing late-stage surprises? What you’ll learn… What SI/PI means and why it’s essential for 3D IC reliability How 3D design shifts traditional SI/PI workflows and stakeholder roles What progressive verification looks like in practice—from architectural feasibility to detailed modeling How new standards like UCIe and AIB add flexibility—and ambiguity—to the design process The real-world challenges Siemens overcame with Chiplets, a smart substrate startup Where you’ll find it…. What is SI/PI and why does it matter in 3D IC? (1:40) How does the SI/PI flow differ from traditional monolithic designs? (3:20) What is progressive verification, and how does it help? (5:55) Who are the key stakeholders—and why is collaboration essential? (9:20) The story behind Siemens’ partnership with Chiplets (11:35) Final thoughts on the future of 3D IC and SI/PI’s role (14:05) In this episode of the Siemens 3D IC Podcast, host John McMillan sits down with John Caka, Principal SI/PI Engineer at Siemens EDA, to explore why signal and power integrity (SI/PI) analysis is more vital than ever in 3D IC workflows—and why progressive verification is key to managing complexity at every stage of design. Together, they unpack the evolving demands of SI/PI in 3D IC architecture, from early planning to vendor-specific IP verification. You'll learn how multidisciplinary teams—spanning layout, thermal, mechanical, electrical, and packaging—must align in parallel to make next-gen designs successful. This episode also shares behind-the-scenes insight into Siemens’ recent collaboration with Chiplets, highlighting the EDA tool flexibility and scalability needed for today’s massive pin-count designs. Ideal for SI/PI engineers, 3D IC architects, packaging teams, die designers, layout specialists, and system-level verification professionals. Connect with John McMillan LinkedIn Website Connect with John Caka LinkedIn Website
What does “multiphysics” really mean in 3D IC design—and why is it more important than ever to start early? What you’ll discover: Learn how early predictive multiphysics analysis can help prevent thermal, stress, and electrical failures later in the design cycle Understand the collaboration challenges across die, interposer, packaging, and RTL teams—and how to unify them Hear real-world insights on how system-level ownership and EDA platforms reduce risk in complex 3D IC projects Get up to speed on emerging standards like 3D Blocks and 3D PDKs that are shaping the future of chiplet integration Discover how simulation and digital twin strategies enable more accurate system-level behavior modeling In this episode of the Siemens 3D IC Podcast, host John McMillan is joined by returning guest John Ferguson, Senior Director of Product Management for Calibre 3D IC Solutions at Siemens EDA, and first-time guest Tarek Ramadhan, Application Engineering Manager for 3D IC Technical Solutions. Together, they explore why traditional SoC methodologies fall short in the 3D world, how early predictive analysis can save teams from costly late-stage surprises, and why effective collaboration across domains (and companies) is essential. From thermal and stress concerns to data format mismatches and emerging standards like 3D Blocks, this episode delivers powerful insight into future-ready 3D IC design. 👉 Ideal for IC designers, system architects, packaging engineers, RTL and ESD teams, and anyone involved in the transition from 2D to 3D IC workflows. Find what you’re looking for: How is the design process shifting from 2D and 2.5D to 3D IC (2:25) What is multi-physics, and how does it impact 3D IC design? (5:00) The hidden collaboration pitfalls between die, interposer, and packaging teams (7:30) How is it impacting collaboration between companies or within companies and between teams? (10:45) The role of new standards like 3D Blocks and 3D IC PDKs (13:10) How emerging standards like 3D Blocks and 3D IC PDKs are streamlining design workflows (14:30) Final thoughts (16:00) Connect with John McMillan LinkedIn Website Connect with Tarek Ramadan LinkedIn Website Connect with John Ferguson LinkedIn Website
What does it take to turn 3D IC from a buzzword into a successful reality, and how early should you start thinking about system-level planning? Get practical insight into why system-level planning is essential from day one of your 3D IC project. You’ll learn how to avoid costly design iterations, streamline collaboration across domains, and accelerate time to market with co-design and early simulation strategies. In this episode of the Siemens 3D IC podcast, host John McMillan sits down with Tony Mastroianni, Advanced Packaging Solutions Director at Siemens EDA. With decades of experience in design, integration, and manufacturing, Tony shares why system-level planning is a critical first step, not an afterthought, when tackling 3D IC projects. They unpack the common pitfalls of treating package design as isolated from system goals and how the shift from chip-centric to system-centric thinking can redefine success in high-density, high-performance integration. Tony also discusses the value of co-design, early simulation, and cross-disciplinary collaboration to reduce iterations, control cost, and accelerate time to market. If you're involved in semiconductors, EDA tools, IC packaging, or advanced integration, this episode offers clear, actionable insight into the future of electronics design. Recommended for: System architects, IC designers, semiconductor packaging engineers, EDA tool users, design managers, and anyone working on or interested in 3D IC implementation. What You’ll Learn in this Episode: From a dozen transistors per chip to trillions: What 30 years in the industry can teach you. (1:32) How to realize that 3D IC workflows must change within a company. (5:50) What type of resistance can be expected when implementing design or workflow changes? (07:00) What internal changes are required better to address the cross-disciplinary demands of 3D IC system design? (9:30) Final thoughts (23:00) Connect with John McMillan LinkedIn Website Connect with Tony Mastroianni LinkedIn Website As mentioned during the show: Episode 1: An Introduction to 3D IC https://blogs.sw.siemens.com/podcasts/3d-ic/an-introduction-to-3d-ic-ep-1/
Why is thermal analysis no longer an afterthought in 3D IC design—and what is Siemens doing to empower engineers across every step of the process? In this episode of the Siemens EDA Podcast Series on 3D IC chiplet ecosystems, host John McMillan welcomes András Vass-Varnai, 3DIC Solutions Engineer at Siemens Digital Industries, to spotlight one of the most critical (and often underestimated) challenges in modern chip design: thermal analysis. As power densities soar and chiplets stack closer together than ever before, effective thermal management is essential—not just for performance, but for reliability, lifespan, and product feasibility. András explores how Siemens is bridging the gap between design, packaging, and thermal engineering through integrated toolchains and a new generation of digital twins. Whether you're a silicon designer, package architect, or thermal analyst, this episode offers valuable insights into the future of collaborative thermal modeling, IP protection, and real-time simulation integration. What You’ll Learn in this Episode: Andrass Vass-Varnai’s background and current role at Siemens EDA (1:25) How is the shift to 3D IC packaging affecting thermal analysis? (2:35) What is the issue with the current approach to thermal analysis? (4:20) What is the significance of having thermal models for the customers? (6:50) Siemens' vision for the ideal future workflow (11:00) Conclusion and future outlook (17:00) Connect with John McMillan LinkedIn Website Connect with Andras Vass-Varnai LinkedIn Website
Why are companies rapidly adopting fan-out wafer-level packaging (FO-WLP)—and how does this shift impact the traditional chip design process? In this episode of the Siemens 3D IC Podcast Series, host John McMillan is joined by Chris Cone, IC Packaging Product Marketing Manager at Siemens EDA, to explore how fan-out wafer-level packaging is transforming advanced semiconductor packaging workflows. Chris shares his journey from analog design engineer to packaging and automation expert, and breaks down the growing need for intelligent, automated workflows that support the increasing complexity and size of modern designs. They discuss how new IC packaging techniques demand more automation, design iteration, and cross-functional collaboration than ever before—and why building a replayable, flexible automation language is the key to faster, scalable design success. Whether you're a layout engineer, SI/PI analyst, or replay coordinator, this episode will show you how to streamline your process using a common design framework and why human-readable automation is the next big leap in fan-out design. What You’ll Learn in this Episode: Chris Cone’s journey from analog IC designer to Siemens EDA packaging lead (1:10) What is fan-out wafer-level packaging, and why is it gaining traction? (1:50) How FOWLP is different than a traditional BGA design process (2:30) The four major phases in a fan-out packaging workflow, from tech setup to final verification (3:45) What is the impact on different roles, such as a package designer, layout designer, engineer, signal integrity, power, and integrity analysis? (8:00) The three essential traits of successful design automation (10:00) Key takeaways from real-world projects using Siemens’ automated packaging flows (11:45) Connect with John McMillan LinkedIn Website Connect with Chris Cone Website
As 3DIC adoption ramps up, it’s becoming clear: microarchitecture needs a rethink. So how do you design hardware that can survive and thrive in the new era of stacked silicon? In this episode of the Siemens 3D IC Podcast, host John McMillan speaks with Pratyush Kamal, Director of R&D for 3D IC Solutions Engineering at Siemens Digital Industries. With decades of experience spanning Qualcomm and Google, Pratyush brings deep insight into the evolution of IC design—and how 3D integration is transforming every layer of the design stack. From redefining how and when microarchitecture decisions are made to overcoming the thermal, testing, and failure analysis challenges that come with 3D stacking, this episode dives into the critical topics design teams need to understand today. You’ll also hear how AI, automation, and cross-disciplinary expertise are reshaping team roles—and why software-defined silicon is redefining the design process itself. This episode is essential listening for IC architects, system designers, and packaging engineers navigating the transition to advanced 3D IC platforms. What You’ll Learn in this Episode: What is microarchitecture in IC design? (2:30) What does microarchitecture mean in 3D IC design? (3:20) How early do we need to consider microarchitecture in 3D IC design? (4:45) The main issues system designers face concerning the increasing complexity of microarchitecture (5:50) How are roles changing to enable a more holistic outlook on 3D IC microarchitecture? (9:15) What would enable non-silo design practice? (11:00) Closing thoughts (11:55) Connect with John McMillan LinkedIn Website Connect with Pratyush Kamal LinkedIn Website Explore More on 3D IC Innovation & Research: Deepen your understanding of 3D IC design with these valuable resources: Home | UCIe Consortium Die Stacking (3D) Microarchitecture | IEEE Conference Publication | IEEE Xplore Fine grain 3D integration for microarchitecture design through cube packing exploration | IEEE Conference Publication | IEEE Xplore Opportunities, Challenges and Mitigations in 3DIC Design, Test, and Analyses | IEEE Conference Publication | IEEE Xplore Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools | IEEE Journals & Magazine | IEEE Xplore
How are 3D Integrated Circuits (3D ICs) revolutionizing semiconductor design, and what role do advanced packaging technologies play in this transformation? In this episode of the Siemens EDA Podcast Series on 3D IC chiplet ecosystems , host John McMillan sits down with Jan Vardaman, President and Founder of TechSearch International, to discuss the latest advancements in 3D IC technology, heterogeneous integration, and advanced semiconductor packaging. Jan shares insights on why 3D ICs are gaining traction, the key industry drivers behind their adoption, and how companies are overcoming integration challenges. She also explores the role of chiplets, AI-driven design processes, and supply chain shifts in shaping the future of semiconductor manufacturing. Whether you're a semiconductor engineer, a tech enthusiast, or a business leader looking to stay ahead in the industry, this episode is packed with valuable insights into the next generation of IC design. What You’ll Learn in this Episode: The main drivers for advanced integration ( heterogeneous or homogeneous silicon) from a technology and business point of view. (02:10) Specific market segments and industries that are driving these advanced integrations, including chiplet designs ( 3:10 ) The different needs and requirements for packaging ( 6:50 ) How different substrate materials (silicon, RDL, glass core, organic interposer bridges, etc.) compete and complement each other in specific applications ( 8:20 ) Siemens’ Innovator3D IC Platform (10:55) Connect with John McMillan LinkedIn Website Connect with Jan Vardaman LinkedIn Website
One of the best ways to speed-up product development is to integrate test as early as possible in the design cycle. This shift-left strategy becomes even more critical when advanced IC designs evolve from a single die per package to complex systems with multiple dies integrated into a package. These 2.5D and 3D multi-die design strategies pose some interesting challenges and opportunities for test. Today, David Lyell interviews Joe Reynick, the Tessent Product Engineering Manager for Siemens EDA. He’ll help us to understand the complexity of development tests for 3D and 2.5D packages. In this episode, you’ll learn about the challenges of performing comprehensive tests on 3D and 2.5D designs. You’ll also hear about the factors that you need to consider while planning for 3D DFT and IP tests. Additionally, you’ll hear about how 2.5D tests and 3D tests can complement each other. What You Will Learn In This Episode: The things you need to be aware of when doing 2.5D and 3D tests (03:34) The DFT and IP test methods that the DFT and IP test team should implement (09:36) The die and package level planning interactions needed for 3D DFT and IP test (11:22) Factors to consider while doing 3D tests (14:20) What is involved in multi-die IP core test (16:00) Connect with Joe Reynick: LinkedIn Connect with David Lyell: LinkedIn Hosted on Acast. See acast.com/privacy for more information.
3D IC designs are complex puzzles that engineers have to solve to achieve high performance and reliability. While vertical stacking gives more design options, it also increases the possible number of defective arrangements. There is no one-design-fits-all in 3D IC; engineers must understand their needs and create designs that meet them. Today, John McMillan interviews John Ferguson, Product Management Director of Calibre DRC Technologies at Siemens Digital EDA. He’ll help us understand the complexity of 3D IC designs and how it impacts their reliability. In this episode, you’ll learn about some of the guardrails that increase the reliability of 3D IC devices. You’ll also hear about some of the common challenges an engineer has to solve while designing such devices. Additionally, you’ll get some tips on where to start with 3D IC designs to minimize cost and maximize performance. What You Will Learn in this Episode: Improving the reliability of heterogeneous assemblies (01:36) Solving the heat problem in heterogeneous assemblies (07:46) The sources of mechanical stress in 3D IC assemblies and how to address them (14:44) Where to start when designing 3D IC devices (22:07) Connect with John Ferguson: LinkedIn Connect with John McMillan: LinkedIn Hosted on Acast. See acast.com/privacy for more information.
A common challenge faced when actualizing new technologies such as 3D IC is the lack of specialized tools to mass assemble them. That’s because their designs are normally developed by R&D teams that view commercialization as someone else’s task. At the moment, organizations are working to create and perfect the tools need to assemble 3D IC chips. Today, John McMillan interviews John Ferguson, Director of Product Management, Dusan Petranovic, Principal Technologist, and Steve McKinney, Account Technology Manager. They’ll help us understand what a 3D IC verification workflow might look like. In this episode, you’ll learn about the challenges associated with 3D IC integration and the components required to make it possible. You’ll also learn about the upgrades that have to be made to make 3D IC assembly possible. Additionally, you’ll hear about parasitic extraction and the tools available to execute it. What You Will Learn In This Episode: Challenges faced in the manufacture of 3D IC chips (02:01) How to ensure that a 3D IC assembly line is aligned (04:18) The challenges of integrating 3D IC (10:55) The tools needed to make 3D IC integration possible (13:56) Connect with Dusan Petranovic: LinkedIn Connect with Steve McKinney: LinkedIn Connect with John McMillan: LinkedIn Hosted on Acast. See acast.com/privacy for more information.
One of the challenges of designing 3D IC chips is getting data from different sources in different formats to work together. You also need a solution that allows you to verify different components such as the interposer, the package, and the die together. Siemens solution allows you to combine data from different sources and handle the verification process collectively. Today, John McMillan interviews Mike Walsh, Technical Applications Engineering Director of the Technical Solutions Sales Team at Siemens Digital EDA. He’ll help understand what a 3D IC physical design workflow might look like. In this episode, you’ll learn about the challenges associated with 3D IC physical design. You’ll also learn about how Siemens solution enables design teams to use data received in different formats. Additionally, you’ll learn why it's important to keep verification in mind early on in the design process. What You Will Learn in this Episode: The challenges faced in the 3D IC physical design phase (01:33) The importance of a design solution that can deal with multiple data formats (03:39) How Siemens helps organizations combine data from different sources in different formats (07:55) The different aspects of 3D IC design flow (12:06) Connect with Mike Wash: LinkedIn Connect with John McMillan: LinkedIn Hosted on Acast. See acast.com/privacy for more information.
For 3D IC to achieve its full potential there is a need to utilize cost-effective front-end design approaches. This is because different microarchitectures will result in different physical sizes, power performance, and cost of production. One of the solutions that have been successfully deployed is the high-level predictive analysis which helps in figuring out optimal architectures for specific cases. In this episode, John McMillan interviews Anthony Mastroianni, the 3D IC Solutions Architect Director at Siemens Digital Industries Software. And, Gordon Allan, Product Manager for Verification IP Solutions at Siemens EDA. They’ll help us understand 3D IC front-end aspects and the latest developments in this field. In this episode, you’ll learn how predictive analytics can be utilized to make 3D IC design faster and cheaper. You’ll also learn what 3D IC front-end design involves and the best way of approaching it. Additionally, you’ll hear about what Siemens is doing to contribute towards making the design process more efficient. What You Will Learn in this Episode: The role of predictive analytics in the front-end design of 3D IC (03:03) How 3D IC packaging should be approached (08:35) The design aspects enabled by 3D IC (12:06) What Siemens is doing to help in front-end 3D IC design (14:50) Connect with Gordon Allan: LinkedIn Connect with Anthony Mastroianni: LinkedIn Connect with John McMillan: LinkedIn Hosted on Acast. See acast.com/privacy for more information.
In most cases, it’s very expensive to get game-changing technological advancements in electrical components to the market. This is because they also require the advancement of the existing design workflows and tools. This barrier has slowed down and even completely stopped the possible mass production of many revolutionary devices. 3D IC is not exempt from this challenge - that’s why several large companies have invested heavily in the development of new package design flows and tools to handle it. In this episode, John McMillan interviews Anthony Mastroianni, the 3D IC Solutions Architect Director at Siemens Digital Industries Software. He has been in the semiconductor industry for over 30 years, primarily in the design of custom integrated circuits. He will help us understand the necessary design flow changes needed to make 3D IC a reality. In this episode, you will learn about the differences between traditional semiconductor packaging and 3D IC packaging. You will also hear about the design workflow required to successfully build 3D IC-based devices. Additionally, you will hear about the new tools that are required to successfully create and test such devices. What You Will Learn in this Episode: The difference between 3D IC and traditional semiconductor packaging (01:37) Why 3D IC requires a change in package design flows (03:28) The workflows envisioned for 3D IC (05:57) The new tools required to handle the new workflows (07:47) The most critical 3D IC workflows (11:13) Connect with Anthony Mastroianni: LinkedIn Connect with John McMillan: LinkedIn Hosted on Acast. See acast.com/privacy for more information.
Standardization plays an important role in promoting the mass adoption of new electrical components. For instance, Application-Specific Standard products, known as ASSP components have been broadly adopted by system designers for board-level integration. These devices have standardized models to enable the PCB level, system design ecosystem. Chiplets are an analogous component that can be integrated at the package level. That’s why the 3D IC design community will likely advocate for standardized models to be adopted by prospective chiplet vendors. In this episode, John McMillan interviews Anthony Mastroianni, the 3D IC Solutions Architect Director at Siemens Digital Industries Software. He is also a member of the Chiplet Design Exchange, whose charter is to standardize chiplet models and deliverables. He will help us understand the application of 3D IC and the need for standard chiplet models. In this episode, you will find out how the 3D IC technology is being utilized and the impact it is having. We will also discuss what the future holds for this new methodology and the steps that need to be made to drive its adoption. Lastly, you will learn about the progress being made in standardizing chiplet models and the need for defined workflows to facilitate a chiplet ecosystem. What You’ll Learn in this Episode: Types of applications and packaging technologies currently deploying 3D IC methodologies (01:37) Where the industry is heading in terms of 3D IC adoption (05:08) The types of chiplets available today (05:51) The role of Chiplet Design Exchange in driving 3D IC adoption (07:37) Connect with Anthony Mastroianni: LinkedIn Connect with John McMillan: LinkedIn Hosted on Acast. See acast.com/privacy for more information.
Electronic circuits design has become more complex due to the consumers’ need for more features that require more processing capability. To keep up with these demands, new methodologies of designing and connecting chips have been developed. The latest innovation in this area is the three-dimensional integrated circuits (3D IC), which take less space and deliver much higher performance compared to traditional monolithic technologies. In this episode, John McMillan interviews Anthony Mastroianni, the 3D IC Solutions Architect Director at Siemens Digital Industries Software. He has been in the semiconductor industry for over 30 years, primarily in the design of custom integrated circuits. He’ll help us understand the 3D IC technology and the impact it’s expected to have. In this episode, you’ll learn about the current chip standards in the industry and where they fall short. You’ll also learn how 3D IC works and how it will help in solving most of the challenges facing today’s chips. Additionally, you’ll hear about the challenges that come with 3D IC and how some of them are being resolved. What You’ll Learn in this Episode: The problem that 3D IC solves (01:49) How 3D IC works and why it gives tremendous performance (06:37) The difference between 3D IC and other technologies (10:22) The challenges in moving to 3D IC (15:56) Connect with Anthony Mastroianni: LinkedIn Hosted on Acast. See acast.com/privacy for more information.