In this episode of Tech Threads: Weaving the Intelligent Future, Baya Systems Founder and CEO Sailesh Kumar joins AdoreSys Founder and CEO KengSu Teoh to discuss the companies’ new partnership and what it means for semiconductor customers across China and the broader Asia-Pacific region.Hosted by Nandan Nayampally, the conversation explores the rapid growth of custom silicon, the increasing importance of data movement and interconnect technology, and how Baya and AdoreSys are combining complementary strengths to support complex SoC and chiplet designs.From Technology Adoption to ImplementationSailesh and KengSu discuss how Baya and AdoreSys can combine their complementary strengths to support customers across the design journey, from evaluating advanced interconnect technology to silicon implementation.Inside the Conversation• Why data movement and connectivity are becoming defining challenges in modern computing systems• How the shift toward custom silicon is changing customer requirements and development models• Why chiplet architectures create new opportunities and new connectivity challenges• What semiconductor design teams in China value when evaluating and adopting technology• How local engineering relationships can accelerate technical engagement and customer support• What Baya Systems and AdoreSys hope to accomplish through their partnership
As AI models grow larger and more autonomous, every query requires extraordinary volumes of data to move quickly between memory and compute, making data movement one of the defining challenges for next-generation AI infrastructure.In this episode of Tech Threads, Nandan Nayampally speaks with Srujan Linga, CEO and co-founder of Kandou AI, about why the industry’s so-called “memory wall” is actually a multidimensional “memory maze,” shaped by different requirements for bandwidth, latency and capacity.They explore the limitations of relying exclusively on high-bandwidth memory, the untapped potential of copper interconnects, and how technologies such as Chord Signaling and Copper MIMO can increase bandwidth while reducing power and extending reach. The conversation also examines where copper and optics can complement one another, how advanced interconnects could turn an entire PCB into a larger multi-chip system, and why the economics and scalability of AI infrastructure must be considered alongside raw performance.The result is a system-level perspective on what it will take to build more efficient, scalable and accessible AI infrastructure.
Europe has the technical talent and research base to compete in advanced semiconductor design. Turning that into globally competitive AI and HPC systems takes more than investment. It needs scalable architectures, open ecosystems, and real collaboration across the supply chain.In this episode of Tech Threads, Baya’s CCO, Nandan Nayampally talks with Cesc Guim, CEO of Openchip, about building next-generation processors and computing platforms in Europe, why chiplet-based design is becoming central to scalable, specialized architectures, and how RISC-V opens up flexibility that fixed-ISA approaches can't match.They also dig into the hardest problem in modern system design: moving data efficiently between processors, accelerators, memory, and chiplets. At scale, performance depends less on adding compute and more on getting the interconnect right: bandwidth, latency, and efficiency for demanding AI workloads.Cesc also shares his take on the challenges and opportunities and the thrill of building a semiconductor company in Europe, forming the right technology partnerships, and turning regional ambition into products that compete globally.In this episode:• How Openchip is approaching AI and HPC system design• Why chiplets are becoming central to scalable, specialized architectures• Where RISC-V fits in enabling open, differentiated designs• Why interconnect performance is the bottleneck for AI system efficiency• How partnerships, especially with critical pieces like Baya’s IP, cut complexity, risk, and time-to-market• What Europe needs to convert semiconductor investment into competitive products
In this episode of Tech Threads: Weaving the Intelligent Future, Baya Systems’ Nandan Nayampally sits down with Charlie Cheng, founder and CEO of TC Lab, for an in-depth conversation on the memory wall and why it has become one of the defining bottlenecks in AI infrastructure. While memory constraints have existed for decades, AI inference is bringing the issue into sharper focus by turning memory bandwidth into a direct driver of user experience, system performance, and data center economics.Charlie shares his perspective on the industry’s shift toward alternative AI architectures, from high-bandwidth memory and SRAM-based approaches to emerging 3D memory technologies and hybrid-bonded architectures that bring memory much closer to compute. He explains why inference workloads, especially token generation and KV cache access, can quickly become bandwidth-bound, and why solving that challenge requires rethinking the relationship between compute, memory, packaging, and on-chip data movement.The discussion also explores what happens when memory bottlenecks are reduced or removed. As more bandwidth becomes available to AI accelerators, the pressure shifts to the rest of the system, including networks-on-chip, chiplet fabrics, and data movement architectures. For companies building next-generation AI chips, hyperscale infrastructure, autonomous systems, and edge inference platforms, this creates both a challenge and an opportunity: the need for more flexible, scalable, and software-defined approaches to moving data efficiently across increasingly complex systems.Tune in for an expert look at why the future of AI performance depends as much on memory innovation and data movement as it does on compute, and how new architectures could help unlock faster, more efficient, and more scalable AI systems.
In this episode of Tech Threads, Nandan Nayampally, Baya Systems CCO, sits down with Ian Ferguson, Vice President of Vertical Markets and Business Development at SiFive, to unpack one of the most important shifts happening in modern computing: AI is no longer just about scaling compute, it’s about orchestrating complexity.As architectures fragment across accelerators, chiplets, and custom silicon, the real challenge is no longer building faster chips. it’s turning all of these elements into a cohesive, high-performance system.This conversation explores why the industry is moving beyond the traditional “CPU vs GPU” narrative and toward a system-level approach where performance is defined by how effectively compute, memory, interconnect and software work together.From the growing momentum behind RISC-V to the rise of heterogeneous compute environments, the discussion highlights a clear trend: the future won’t be defined by a single dominant architecture, but by optimized combinations of technologies tailored to specific workloads.That shift introduces a new layer of complexity.Key themes explored in this episode include:- Why data movement is emerging as the primary constraint in AI systems- How efficiency metrics like “tokens per dollar” are reshaping design priorities- The shift toward purpose-built architectures across data center, automotive, and edge applications- The role of open ecosystems and interoperability in accelerating innovation- Why competitive advantage is shifting from individual components to full system designIf you’re interested in where AI is headed, this is a must-watch conversation on the forces shaping the future of compute and what it takes to stay ahead.