EE Times Current

IMChip’s founders say interface memristors are more reliable and scalable than filamentary ones. The Groningen spin-out grows the devices at high temperature, then transfers them onto silicon. In this month’s Brains and Machines, Sunny Bains talks with Tamalika Banerjee, chief scientific officer, and Ruben Hamming-Green, head of R&D, about their plan for an edge-AI prototype chip within two years. Giulia D’Angelo of the Czech Technical University in Prague and Ralph Etienne-Cummings of Johns Hopkins University join the discussion.

As AI-driven SoCs move to advanced process nodes, design complexity, development cost, and execution risk are rising sharply. In this episode, Synopsys Executive Director of Product Management Ravi Todi explains why competitive power, performance, and area (PPA) are no longer sufficient on their own. Success in the AI era also depends on predictable execution and disciplined management of total cost of ownership (TCO) across the full SoC lifecycle.The discussion highlights how a holistic, silicon-proven Foundation IP platform—delivered as an integrated solution from a single trusted partner—can help reduce risk early, minimize integration issues and re-spins, accelerate yield ramp, and deliver differentiated PPA for high-performance compute AI, and edge AI designs. Ravi also explores how deep foundry alignment and EDA co-optimization reveal the true cost of fragmented IP sourcing beyond license price, enabling teams to meet demanding market requirements, achieve faster and more predictable tape-outs, and lower overall SoC TCO.

In this month's Brains and Machines, Dr. Ryad Benosman discusses event-based vision, retinal prosthetics, and neuromorphic startups with Dr. Sunny Bains of University College London. A co-founder of Prophesee, he explains why he believes AI's future must come from neuromorphic engineering. Discussion follows with Dr. Giulia D’Angelo from the Czech Technical University in Prague and Professor Ralph Etienne-Cummings of Johns Hopkins University. 

As systems become more software-defined, the traditional development model of waiting for hardware before serious software validation begins is no longer sustainable. Software teams need platforms earlier. Hardware teams need realistic workloads sooner. Verification teams need better ways to expose system-level issues before tapeout. We will look at how digital twins are becoming the shared foundation for this new HW/SW co-development model. Using virtual platforms, hardware emulation, and FPGA prototyping, teams can start earlier, collaborate more closely, and design/optimize/validate with greater confidence. We will also discuss new system-level verification challenges in power, performance, and DFT, showing how pre-silicon Hardware platforms can help teams find critical issues earlier and deliver more robust software-defined systems.

Artificial intelligence is accelerating semiconductor development, but more compute, more automation, and more engineering data do not automatically create better decisions. As design and manufacturing workflows become increasingly AI-enabled, a new constraint is emerging: trust. In this episode, Dr. Jim Shiely builds on themes from his Patterning the Singularity leadership work to explore the semiconductor industry’s “trust bottleneck” and why trustworthy engineering intelligence is becoming essential to future innovation.