From Tape-Out to Co-Design: The Evolution of 3DIC Technologies
Description
Pratyush Kamal explains how 3DIC technologies are transforming semiconductor design as Moore's Law slows, requiring closer integration between chip and package design to maximize performance.
• Traditional chip design treated packaging as an afterthought with designers "throwing designs over the wall"
• Economic realities of advanced nodes mean companies now pay more for smaller transistors, driving chiplet adoption
• Thermal challenges multiply in 3D stacks as power density doubles with each added layer
• Data centers projected to consume 10% of US electricity by 2030, making power efficiency critical
• Siemens working to standardize design languages across tools and enable open chiplet ecosystems
• Average age of electrical engineers in US is 57, creating urgent need for workforce development
• Universal Chiplet Interconnect Express (UCIe) emerging as key standard for chiplet interoperability
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